Testability of Combinational and Sequential Circuits by Fault Injection Technique

Published Date: 31-03-2017

DOI: 10.24128/IJRAER.2017.HI89uv

Author(s) :

S. Ravi, G.Balu, M.Kannan, S. Ashik Ahamed, K. Kavin Kumar

Volume/Issue :
Volume 3 / Issue 3 (03-2017)
Abstract :

Testing combinational and sequential blocks can be actually done easily. However, testing a complex circuit requires set of known test patterns and their corresponding responses to be stored in memory. Also, some of the internal nodes of the circuits cannot be accessed easily to apply desired input values at that node. This paper presents a fault injection technique to inject transient and permanent fault at the Verilog code description of both combinational and sequential digital circuits. The proposed method can verify the testability of the circuits using both offline and online testing. The proposed method is tested with two combinational circuits (8- Bit Adder and a benchmark circuit called, C17) and two sequential circuits (8 – Bit Counter and S27 Benchmark Circuit) for Injection of permanent fault and transient faults and their testabilities are evaluated.

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